For a clock frequency larger than a value e.g., 1 GHz, in a continuous-time delta-sigma modulator, the stability issue due to parasitic capacitance from a quantizer or excess loop delay (ELD) compensation path becomes troublesome. In addition, in the high bandwidth application, an oversampling ratio (OSR) is generally not enough and non-ideal effect may occur to lower the stability, therefore, a high bit-number quantizer (e.g. 5-bit quantizer) is used to improve the performance and stability. However, using the high bit-number quantizer may induce a heavy input load (e.g. parasitic capacitance), and an extra pole may be generated due to the input load, which influences the stability of the circuit and increases design efforts.